R
XC1800 Series of In-System Programmable Configuration PROMs
pulse from the FPGA. OE/RESET is connected to an exter-
nal resistor to pull OE/RESET HIGH releasing the FPGA
INIT and allowing configuration to begin. OE/RESET is
held low until the XC1800 voltage reaches the operating
voltage range. If the power drops below 2.0 Volts, the
PROM will reset.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tol-
erant even through the core power supply is 3.3 volts. This
allows 5V CMOS signals to connect directly to the PROM
inputs without damage. In addition, the 3.3V VCC power
supply can be applied before or after 5V signals are applied
to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,
the core power supply (VCC), and the output power supply
(VCCO) may have power applied in any order. This makes
the PROM devices immune to power supply sequencing
issues.
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high imped-
ance state regardless of the state of the OE input. JTAG
pins TMS, TDI and TDO can be 3-state or high.
Reset Activation
On power up, OE/RESET is held low until the XC1800 is
active (1ms) and able to supply data after receiving a CCLK
Table 6: Truth Table for PROM Control Inputs
Control Inputs
Outputs
Internal Address
OE/RESET
Low
CE
Low
DATA
active
CEO
High
Icc
active
if address < TC: increment
if address > TC: don’t change
3-state
3-state
3-state
3-state
Low
High
High
High
reduced
High
Low
High
Low
High
High
Held reset
Held reset
Held reset
active
standby
standby
Note: TC = Terminal Count = highest address value. TC+1 = address 0.
September 17, 1999 (Version 1.3)
11
XILINX [ XILINX, INC ]
