R
XC1800 Series of In-System Programmable Configuration PROMs
Pin
Name
CEO
Boundary
Scan
Order
13
14
44-pin
VQFP
21
44-pin
PLCC
27
20-pin
SOIC & PLCC
13
Function
Pin Description
DATA OUT Chip Enable (CEO) output is connected
to the CE input of the next PROM in the
OUTPUT
chain. This output is Low when the CE
ENABLE
and OE/RESET inputs are active AND
the internal address counter has been in-
cremented beyond its Terminal Count
(TC) value. When the PROM has been
read, CEO will follow CE as long as OE/
RESET is High. When OE/RESET goes
Low, CEO stays High until the PROM is
brought out of reset by bringing OE/RE-
SET High. CEO can be programmed to
be either active High or active Low.
GND is the ground connection.
MODE
SELECT
The state of TMS on the rising edge of
TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic 1 to the de-
vice if the pin is not driven.
This pin is the JTAG test clock. It se-
quences the TAP controller and all the
JTAG test and programming electronics.
This pin is the serial input to all JTAG in-
struction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic 1 to the system if the pin is
not driven.
GND
TMS
6, 18, 28 &
41
5
3, 12, 24 &
34
11
11
5
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT This pin is the serial output for all JTAG
instruction and data registers. TDO has
an internal 50k ohm resistive pull-up on it
to provide a logic 1 to the system if the pin
is not driven.
Positive voltage supply of 3.3V for inter-
nal logic and input buffers.
Positive voltage supply connected to the
output voltage drivers.
31
37
17
V
CC
V
CCO
17, 35 & 38 23, 41 & 44
8, 16, 26 & 14, 22, 32 &
36
42
18 & 20
19
*Programmable for Serial Mode only on 18512 and 1801.
September 17, 1999 (Version 1.3)
3
XILINX [ XILINX, INC ]
