R
XC1800 Series of In-System Programmable Configuration PROMs
Pinout and Pin Description
Table 1: Pin Names and Descriptions
Pin
Name
D0
Boundary
Scan
Order
4
3
D1
6
5
D2
2
1
D3
8
7
D4
24
23
D5
10
9
D6
17
16
D7
14
13
CLK
0
Function
Pin Description
44-pin
VQFP
40
44-pin
PLCC
2
20-pin
SOIC & PLCC
1
DATA OUT D0 is the DATA output pin to provide data
for configuring an FPGA in serial mode.
OUTPUT
ENABLE
DATA OUT D0- D7 are the output pins to provide par-
allel data for configuring a Xilinx FPGA in
OUTPUT
express mode.
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA IN
Each rising edge on the CLK input incre-
ments the internal address counter if both
CE is low and OE/RESET is high.
29
35
16
42
4
2
27
33
15
9
15
7*
25
31
14
14
20
9
19
25
12
43
5
3
20
OE/
RESET
19
18
CE
15
When Low, this input holds the address
counter reset and the DATA output at
DATA OUT
high impedance.
OUTPUT
ENABLE
DATA IN
When CE is High, this pin puts the device
into standby mode. The DATA output pin
is at High impedance, and the device is in
low power standby mode.
DATA IN
13
19
8
15
21
10
CF
22
21
DATA OUT Allows JTAG CONFIG instruction to ini-
tiate FPGA configuration without power-
DATA IN
ing down FPGA.
10
16
7*
2
September 17, 1999 (Version 1.3)
XILINX [ XILINX, INC ]
