R
Functional Description
Date
Version
3.2.1
3.3
Revision
Corrected various typos and incorrect links.
05/30/06
10/02/06
Clarified that the block RAM Readback feature is available either on the -5 speed grade or
the Industrial temperature range.
11/09/06
3.4
Updated the description of the Input Delay Functions. The ODDR2 flip-flop with C0 or C1
Alignment is no longer supported. Updated Figure 5. Updated Table 6 for improved PCI
input voltage tolerance. Replaced missing text in Clock Buffers/Multiplexers. Updated SPI
Flash devices in Table 53. Updated parallel NOR Flash devices in Table 61. Direct, SPI
Flash in-system Programming Support was added beginning with ISE 8.1i iMPACT
software for STMicro and Atmel SPI PROMs. Updated Table 71 and Table 72 as Stepping
1 is in full production. Freshened various hyper links. Promoted Module 2 to Production
status.
03/16/07
3.5
Added information about new Spartan-3 Generation user guides (Design Documentation
Available). Added cross-references to UG331: Spartan-3 Generation FPGA User Guide
and to UG332: Spartan-3 Generation Configuration User Guide. Added note about possible
JTAG configuration issues when the FPGA mode pins are set for Master mode and using
software prior to ISE 9.1.01i (JTAG Mode). Removed a few lingering references to “weak”
pull-up resistors, including in Figure 12. Removed vestigial references regarding the
LDC[2:0] and HDC pins during Slave Parallel Mode configuration. These pins are not used
in this configuration mode.
05/29/07
04/18/08
3.6
3.7
Added information about HSWAP and PCI differences between steppings to Table 71.
Removed “Performance Differences between Global Buffers” to match improved specs in
Module 3. Updated PROG_B pulse width descriptions to match specification in Module 3.
Corrected Figure 6 to show six taps and updated associated text. Added note for
recommended pull-up on DONE in Table 55 and elsewhere. Added a caution regarding
Persist of pins A20-A23. Updated Stepping description in Table 71 to note that only
Stepping 1 is in production today. Updated links.
08/26/09
3.8
Added a frequency limitation to Equation 6, page 57. Added a new Equation 7, page 57 with
a frequency limitation. Added a Spread Spectrum, page 58 paragraph. Added Table 42,
page 62. Updated a Flash vendor name in Table 61, page 90. Removed the < symbol from
the flash read access times in Table 62, page 90. Revised the first paragraph in
Configuration Sequence, page 103. Revised the first paragraph in Power-On Behavior,
page 112. Revised the second paragraph in Production Stepping, page 113. Revised the
first paragraph in Ordering a Later Stepping, page 113.
116
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DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
