R
XC17V00 Series Configuration PROMs
X-Ref Target - Figure 3
OPTIONAL
Daisy-chained
FPGAs with
different
DOUT
V
CC
configurations
4.7K
FPGA
OPTIONAL
V
CC
Slave FPGAs
with identical
configurations
4.7K
(1)
Modes
V
CC
V
CC
V
CC
(2)
V
CC
Vpp
V
CC
Vpp
DATA
CLK
CE
DIN
BUSY
BUSY
First
PROM
CCLK
DATA
CEO
DONE
INIT
Cascaded
PROM
CLK
CE
OE/RESET
OE/RESET
PROGRAM
(Low Resets the Address Pointer)
(1) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
Master Serial Mode
(1)
I/O
(1)
V
V
V
V
I/O
CC
CC
CC
External
Osc
CS
(4)
(3)
Modes
WRITE
1K
1K
3.3V
4.7K
Vpp
Vpp
BUSY
Second
FPGA
CC
V
CC
(2)
BUSY
BUSY
First
PROM
CLK
CLK
CCLK
PROM
8
PROGRAM
CEO
CEO
D[0:7]
DONE
INIT
D[0:7]
CE
D[0:7]
CE
OE/RESET
OE/RESET
(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.
(2) For specific DONE resistor recommendations, refer to the appropriate FPGA data sheet or user guide.
(3) For Mode pin connections, refer to the appropriate FPGA data sheet or user guide.
(4) External oscillator required for FPGA slave SelectMAP modes.
SelectMAP Mode, XC17V16 and XC17V08(1) only.
DS073_03_102708
Figure 3: (a) Master Serial Mode (b) SelectMAP Mode
(dotted lines indicate optional connection)
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
9
XILINX [ XILINX, INC ]
