R
XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
TCEH
CE
T
T
T
HCE
SCE
SCE
RESET/OE(1)
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
OH
CAC
T
CE
DATA
T
T
SBUSY
OH
T
HBUSY
BUSY(2)
Note:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity.
Timing specifications are identical for both polarity settings.
2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time T
during a rising CLK edge, then there is no corresponding change to DATA.
after the rising CLK edge. If BUSY is active (High)
CAC
DS073_05_031606
Symbol
Description
Min
–
Max
15
20
20
35
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TOE
TCE
OE to data delay
CE to data delay
–
TCAC
TDF
CLK to data delay(2)
–
CE or OE to data float delay(3,4)
Data hold from CE, OE, or CLK(4)
Clock periods
–
TOH
0
TCYC
TLC
50
25
25
25
0
–
CLK Low time(4)
–
THC
CLK High time(4)
–
TSCE
THCE
THOE
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
–
–
25
5
–
TSBUSY BUSY setup time
THBUSY BUSY hold time
–
5
–
TCEH
CE High time (guarantees counters are reset)
20
–
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
6. If T
7. If T
High, 2 μs, T = 2 μs.
CEH
HOE
CE
High, 2 μs, T = 2 μs.
OE
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
12
XILINX [ XILINX, INC ]
