R
XC17V00 Series Configuration PROMs
AC Characteristics over Operating Condition for XC17V04, XC17V02, and
XC17V01
X-Ref Target - Figure 4
TCEH
CE
T
T
T
HCE
SCE
SCE
RESET/OE
T
HOE
T
LC
T
HC
T
CYC
CLK
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate
FPGA data sheet or user guide for actual configuration signal sequences.
DS073_04_14102005
Symbol
TOE
Description
Min
–
Max
Units
ns
OE to data delay
CE to data delay
CLK to data delay
30
45
45
50
–
TCE
–
ns
TCAC
TDF
–
ns
CE or OE to data float delay(2,3)
Data hold from CE, OE, or CLK(3)
Clock periods
–
ns
TOH
0
ns
TCYC
TLC
67
25
25
25
0
–
ns
CLK Low time(3)
–
ns
THC
CLK High time(3)
–
ns
TSCE
THCE
THOE
TCEH
CE setup time to CLK (to guarantee proper counting)
CE hold time to CLK (to guarantee proper counting)
OE hold time (guarantees counters are reset)
CE High time (guarantees counters are reset)
–
ns
–
ns
25
20
–
ns
–
ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. If T
6. If T
High, 2 μs, T = 2 μs.
CEH
HOE
CE
High, 2 μs, T = 2 μs.
OE
DS073 (v1.12) November 13, 2008
www.xilinx.com
Product Specification
11
XILINX [ XILINX, INC ]
