R
Spartan and Spartan-XL FPGA Families Data Sheet
The register choice is made by placing the appropriate
library symbol. For example, IFD is the basic input flip-flop
(rising edge triggered), and ILD is the basic input latch
(transparent-High). Variations with inverted clocks are also
available. The clock signal inverter is also shown in Figure 5
on the CK line.
using an option in the bitstream generation software. The
Spartan family output levels are also configurable; the two
global adjustments of input threshold and output level are
independent. The inputs of Spartan devices can be driven
by the outputs of any 3.3V device, if the Spartan family
inputs are in TTL mode. Input and output thresholds are
TTL on all configuration pins until the configuration has
been loaded into the device and specifies how they are to
be used. Spartan-XL family inputs are TTL compatible and
3.3V CMOS compatible.
The Spartan family IOB data input path has a one-tap delay
element: either the delay is inserted (default), or it is not.
The Spartan-XL family IOB data input path has a two-tap
delay element, with choices of a full delay, a partial delay, or
no delay. The added delay guarantees a zero hold time with
respect to clocks routed through the global clock buffers.
(See Global Nets and Buffers, page 12 for a description of
the global clock buffers in the Spartan/XL families.) For a
shorter input register setup time, with positive hold-time,
attach a NODELAY attribute or property to the flip-flop.The
output of the input register goes to the routing channels (via
I1 and I2 in Figure 6). The I1 and I2 signals that exit the IOB
can each carry either the direct or registered input signal.
Supported sources for Spartan/XL device inputs are shown
in Table 4.
Spartan-XL family I/Os are fully 5V tolerant even though the
V
CC is 3.3V. This allows 5V signals to directly connect to the
Spartan-XL family inputs without damage, as shown in
Table 4. In addition, the 3.3V VCC can be applied before or
after 5V signals are applied to the I/Os. This makes the
Spartan-XL devices immune to power supply sequencing
problems.
The 5V Spartan family input buffers can be globally config-
ured for either TTL (1.2V) or CMOS (VCC/2) thresholds,
GTS
T
D
Q
O
OUTPUT DRIVER
Programmable Slew Rate
Programmable TTL/CMOS Drive
(Spartan only)
CK
EC
OK
Package
Pad
I1
I2
INPUT BUFFER
Delay
D
Q
Programmable
Pull-Up/
Pull-Down
Network
IK
CK
EC
Multiplexer Controlled
by Configuration Program
EC
DS060_06_041901
Figure 6: Simplified Spartan/XL IOB Block Diagram
DS060 (v1.8) June 26, 2008
www.xilinx.com
7
Product Specification
XILINX [ XILINX, INC ]
