R
Spartan and Spartan-XL FPGA Families Data Sheet
.
Clock Input
Table 2: CLB Storage Element Functionality
Each flip-flop can be triggered on either the rising or falling
clock edge. The CLB clock line is shared by both flip-flops.
However, the clock is individually invertible for each flip-flop
(see CK path in Figure 3). Any inverter placed on the clock
line in the design is automatically absorbed into the CLB.
Mode
CK
EC
SR
D
Q
Power-Up or
GSR
X
X
X
X
SR
Flip-Flop
Operation
X
X
1*
X
1
X
D
X
X
D
SR
D
Clock Enable
0*
0*
0*
0*
The clock enable line (EC) is active High. The EC line is
shared by both flip-flops in a CLB. If either one is left discon-
nected, the clock enable for that flip-flop defaults to the
active state. EC is not invertible within the CLB. The clock
enable is synchronous to the clock and must satisfy the
setup and hold timing specified for the device.
0
1
0
Q
Latch
Operation
(Spartan-XL)
1*
1*
Q
D
Both
Legend:
X
X
0
0*
X
Q
Set/Reset
The set/reset line (SR) is an asynchronous active High con-
trol of the flip-flop. SR can be configured as either set or
reset at each flip-flop. This configuration option determines
the state in which each flip-flop becomes operational after
configuration. It also determines the effect of a GSR pulse
during normal operation, and the effect of a pulse on the SR
line of the CLB. The SR line is shared by both flip-flops. If
SR is not specified for a flip-flop the set/reset for that flip-flop
defaults to the inactive state. SR is not invertible within the
CLB.
Don’t care
Rising edge (clock not inverted).
SR
0*
Set or Reset value. Reset is default.
Input is Low or unconnected (default
value)
1*
Input is High or unconnected (default
value)
CLB Signal Flow Control
SR
In addition to the H-LUT input control multiplexers (shown in
box "A" of Figure 2, page 4) there are signal flow control
multiplexers (shown in box "B" of Figure 2) which select the
signals which drive the flip-flop inputs and the combinatorial
CLB outputs (X and Y).
GND
GSR
Each flip-flop input is driven from a 4:1 multiplexer which
selects among the three LUT outputs and DIN as the data
source.
SD
D
D
Q
Q
Each combinatorial output is driven from a 2:1 multiplexer
which selects between two of the LUT outputs. The X output
can be driven from the F-LUT or H-LUT, the Y output from
G-LUT or H-LUT.
CK
RD
EC
Control Signals
Vcc
There are four signal control multiplexers on the input of the
CLB. These multiplexers allow the internal CLB control sig-
nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be
driven from any of the four general control inputs (C1-C4 in
Figure 4) into the CLB. Any of these inputs can drive any of
the four internal control signals.
Multiplexer Controlled
by Configuration Program
DS060_03_041901
Figure 3: CLB Flip-Flop Functional Block Diagram
DS060 (v1.8) June 26, 2008
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Product Specification
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