R
Spartan and Spartan-XL FPGA Families Data Sheet
X2
X15
X16
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15
SERIAL DATA IN
Polynomial: X16 + X15 + X2 + 1
1
1
1
1
1
0 15 14 13 12 11 10 9
8
7
6
5
LAST DATA FRAME
CRC – CHECKSUM
Readback Data Stream
Figure 29: Circuit for Generating CRC-16
DS060_29_080400
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
Configuration Sequence
There are four major steps in the Spartan/XL FPGA
power-up configuration sequence.
•
•
•
•
Configuration Memory Clear
Initialization
Configuration
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration
frames and then tests the INIT input.
Start-up
The full process is illustrated in Figure 30.
Configuration Memory Clear
Initialization
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When VCC reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms. The delay is four times as long when in Master
Serial Mode to allow ample time for all slaves to reach a sta-
ble VCC. When all INIT pins are tied together, as recom-
mended, the longest delay takes precedence. Therefore,
devices with different time delays can easily be mixed and
matched in a daisy chain.
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recog-
nized as High, the device samples the MODE pin to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
34
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DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
