R
Spartan and Spartan-XL FPGA Families Data Sheet
A selection of CRC or non-CRC error checking is allowed by
the bitstream generation software. The Spartan-XL family
Express mode only supports non-CRC error checking. The
Table 16: Spartan/XL Data Stream Formats
Express Mode
Serial Modes
(D0...)
(D0-D7)
(Spartan-XL only)
non-CRC error checking tests for
a
designated
Data Type
Fill Byte
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
11111111b
0010b
FFFFh
11110010b
COUNT[23:0](1)
-
Preamble Code
Length Count
Fill Bits
COUNT[23:0]
1111b
Detection of an error results in the suspension of data load-
ing before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
Field Check
Code
-
11010010b
Start Field
0b
11111110b(2)
DATA[n–1:0]
11010010b
VCC
.
Data Frame
DATA[n–1:0]
Cyclic Redundancy Check (CRC) for Configura-
tion and Readback
CRC or Constant xxxx (CRC)
Field Check
or 0110b
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Extend Write
Cycle
-
FFD2FFFFFFh
Postamble
01111111b
FFh
-
Start-Up Bytes(3)
FFFFFFFFFFFFFFh
Legend:
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 16. If a frame data
error is detected during the loading of the FPGA, the config-
uration process with a potentially corrupted bitstream is ter-
minated. The FPGA pulls the INIT pin Low and goes into a
Wait state.
Unshaded
Light
Once per bitstream
Once per data frame
Once per device
Dark
Notes:
1. Not used by configuration logic.
2. 11111111b for XCS40XL only.
3. Development system may add more start-up bytes.
32
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DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
