欢迎访问ic37.com |
会员登录 免费注册
发布采购

DS060 参数 Datasheet PDF下载

DS060图片预览
型号: DS060
PDF下载: 下载PDF文件 查看货源
内容描述: 斯巴达和Spartan- XL FPGA系列数据手册 [Spartan and Spartan-XL FPGA Families Data Sheet]
分类和应用:
文件页数/大小: 83 页 / 770 K
品牌: XILINX [ XILINX, INC ]
 浏览型号DS060的Datasheet PDF文件第16页浏览型号DS060的Datasheet PDF文件第17页浏览型号DS060的Datasheet PDF文件第18页浏览型号DS060的Datasheet PDF文件第19页浏览型号DS060的Datasheet PDF文件第21页浏览型号DS060的Datasheet PDF文件第22页浏览型号DS060的Datasheet PDF文件第23页浏览型号DS060的Datasheet PDF文件第24页  
R
Spartan and Spartan-XL FPGA Families Data Sheet  
connected to GTS. A specific pin location can be assigned  
to this input using a LOC attribute or property, just as with  
any other user-programmable pad. An inverter can option-  
ally be inserted after the input buffer to invert the sense of  
the Global 3-state signal. Alternatively, GTS can be driven  
from any internal node.  
On-Chip Oscillator  
Spartan/XL devices include an internal oscillator. This oscil-  
lator is used to clock the power-on time-out, for configura-  
tion memory clearing, and as the source of CCLK in Master  
configuration mode. The oscillator runs at a nominal 8 MHz  
frequency that varies with process, VCC, and temperature.  
The output frequency falls between 4 MHz and 10 MHz.  
STARTUP  
The oscillator output is optionally available after configura-  
tion. Any two of four resynchronized taps of a built-in divider  
are also available. These taps are at the fourth, ninth, four-  
teenth and nineteenth bits of the divider. Therefore, if the  
primary oscillator output is running at the nominal 8 MHz,  
the user has access to an 8-MHz clock, plus any two of  
500 kHz, 16 kHz, 490 Hz and 15 Hz. These frequencies  
can vary by as much as -50% or +25%.  
GSR  
GTS  
PAD  
Q2  
Q3  
IBUF  
Q1, Q4  
DONEIN  
CLK  
DS060_19_080400  
Figure 19: Symbols for Global Set/Reset  
These signals can be accessed by placing the OSC4 library  
element in a schematic or in HDL code. The oscillator is  
automatically disabled after configuration if the OSC4 sym-  
bol is not used in the design.  
Boundary Scan  
The "bed of nails" has been the traditional method of testing  
electronic assemblies. This approach has become less  
appropriate, due to closer pin spacing and more sophisti-  
cated assembly methods like surface-mount technology  
and multi-layer boards. The IEEE Boundary Scan Standard  
1149.1 was developed to facilitate board-level testing of  
electronic assemblies. Design and test engineers can  
embed a standard test logic structure in their device to  
achieve high fault coverage for I/O and internal logic. This  
structure is easily implemented with a four-pin interface on  
any boundary scan compatible device. IEEE 1149.1-com-  
patible devices may be serial daisy-chained together, con-  
nected in parallel, or a combination of the two.  
Global Signals: GSR and GTS  
Global Set/Reset  
A separate Global Set/Reset line, as shown in Figure 3,  
page 5 for the CLB and Figure 5, page 6 for the IOB, sets or  
clears each flip-flop during power-up, reconfiguration, or  
when a dedicated Reset net is driven active. This global net  
(GSR) does not compete with other routing resources; it  
uses a dedicated distribution network.  
Each flip-flop is configured as either globally set or reset in  
the same way that the local set/reset (SR) is specified.  
Therefore, if a flip-flop is set by SR, it is also set by GSR.  
Similarly, if in reset mode, it is reset by both SR and GSR.  
The Spartan and Spartan-XL families implement IEEE  
1149.1-compatible BYPASS, PRELOAD/SAMPLE and  
EXTEST boundary scan instructions. When the boundary  
scan configuration option is selected, three normal user I/O  
pins become dedicated inputs for these functions. Another  
user output pin becomes the dedicated boundary scan out-  
put. The details of how to enable this circuitry are covered  
later in this section.  
GSR can be driven from any user-programmable pin as a  
global reset input. To use this global net, place an input pad  
and input buffer in the schematic or HDL code, driving the  
GSR pin of the STARTUP symbol. (See Figure 19.) A spe-  
cific pin location can be assigned to this input using a LOC  
attribute or property, just as with any other user-program-  
mable pad. An inverter can optionally be inserted after the  
input buffer to invert the sense of the GSR signal. Alterna-  
tively, GSR can be driven from any internal node.  
By exercising these input signals, the user can serially load  
commands and data into these devices to control the driving  
of their outputs and to examine their inputs. This method is  
an improvement over bed-of-nails testing. It avoids the need  
to over-drive device outputs, and it reduces the user inter-  
face to four pins. An optional fifth pin, a reset for the control  
logic, is described in the standard but is not implemented in  
the Spartan/XL devices.  
Global 3-State  
A separate Global 3-state line (GTS) as shown in Figure 6,  
page 7 forces all FPGA outputs to the high-impedance  
state, unless boundary scan is enabled and is executing an  
EXTEST instruction. GTS does not compete with other rout-  
ing resources; it uses a dedicated distribution network.  
The dedicated on-chip logic implementing the IEEE 1149.1  
functions includes a 16-state machine, an instruction regis-  
ter and a number of data registers. The functional details  
can be found in the IEEE 1149.1 specification and are also  
discussed in the Xilinx application note: "Boundary Scan in  
FPGA Devices."  
GTS can be driven from any user-programmable pin as a  
global 3-state input. To use this global net, place an input  
pad and input buffer in the schematic or HDL code, driving  
the GTS pin of the STARTUP symbol. This is similar to what  
is shown in Figure 19 for GSR except the IBUF would be  
20  
www.xilinx.com  
DS060 (v1.8) June 26, 2008  
Product Specification