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Spartan and Spartan-XL FPGA Families Data Sheet
and Spartan-XL families, speeding up arithmetic and count-
ing functions.
and control inputs with the function generators. The carry
outputs connect to the function generators, where they are
combined with the operands to form the sums.
The carry chain in 5V Spartan devices can run either up or
down. At the top and bottom of the columns where there are
no CLBs above and below, the carry is propagated to the
right. The default is always to propagate up the column, as
shown in the figures. The carry chain in Spartan-XL devices
can only run up the column, providing even higher speed.
Figure 17, page 19 shows the details of the Spartan/XL
FPGA carry logic. This diagram shows the contents of the
box labeled "CARRY LOGIC" in Figure 16.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
Figure 16, page 18 shows a Spartan/XL FPGA CLB with
dedicated fast carry logic. The carry logic shares operand
DS060 (v1.8) June 26, 2008
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17
Product Specification
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