R
Virtex-II Platform FPGAs: Functional Description
Routing
ing resources are segmented to offer the advantages of a
hierarchical solution. Virtex-II logic features like CLBs,
IOBs, block RAM, multipliers, and DCMs are all connected
to an identical switch matrix for access to global routing
resources, as shown in Figure 47.
DCM Locations/Organization
Virtex-II DCMs are placed on the top and bottom of each
block RAM and multiplier column. The number of DCMs
depends on the device size, as shown in Table 24.
Table 24: DCM Organization
Device
XC2V40
Columns
DCMs
Switch
Matrix
2
2
4
4
4
4
4
6
6
6
6
4
4
Switch
Matrix
CLB
IOB
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
8
Switch
Matrix
8
8
18Kb
MULT
Switch
Matrix
BRAM
18 x 18
8
Switch
Matrix
8
12
12
12
12
Switch
Matrix
DCM
Switch
Matrix
DS031_55_022205
Figure 47: Active Interconnect Technology
Active Interconnect Technology
Local and global Virtex-II routing resources are optimized
for speed and timing predictability, as well as to facilitate IP
cores implementation. Virtex-II Active Interconnect Technol-
ogy is a fully buffered programmable routing matrix. All rout-
Each Virtex-II device can be represented as an array of
switch matrixes with logic blocks attached, as illustrated in
Figure 48.
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
DCM
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
DS031_34_022205
Figure 48: Routing Resources
DS031-2 (v3.5) November 5, 2007
Product Specification
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