R
Virtex-II Platform FPGAs: Functional Description
until CLK1 transitions High to Low.
When CLK1 transitions from High to Low, the output
switches to CLK1.
BUFGCE
•
•
I
O
No glitches or short pulses can appear on the output.
CE
DS031_62_101200
Wait for Low
Figure 42: Virtex-II BUFGCE Function
S
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.
I0
Switch
I1
OUT
DS031_46_020604
BUFGMUX
Figure 44: Clock Multiplexer Waveform Diagram
BUFGMUX can switch between two unrelated, even asyn-
chronous clocks. Basically, a Low on S selects the I0 input,
a High on S selects the I1 input. Switching from one clock to
the other is done in such a way that the output High and Low
time is never shorter than the shortest High or Low time of
either input clock. As long as the presently selected clock is
High, any level change of S has no effect .
Local Clocking
In addition to global clocks, there are local clock resources
in the Virtex-II devices. There are more than 72 local clocks
in the Virtex-II family. These resources can be used for
many different applications, including but not limited to
memory interfaces. For example, even using only the left
and right I/O banks, Virtex-II FPGAs can support up to 50
local clocks for DDR SDRAM. These interfaces can operate
beyond 200 MHz on Virtex-II devices.
BUFGMUX
I0
O
I1
Digital Clock Manager (DCM)
The Virtex-II DCM offers a wide range of powerful clock
management features.
S
DS031_63_112900
•
Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
Figure 43: Virtex-II BUFGMUX Function
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts driv-
ing the output.
•
•
Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock (I0 or I1). Violating this setup time require-
ment can result in an undefined runt pulse output.
Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.
All Virtex-II devices have 16 global clock multiplexer buffers.
Figure 44 shows a switchover from I0 to I1.
•
•
•
The current clock is CLK0.
S is activated High.
If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see Figure 45). All DCM clock outputs can simul-
taneously drive general routing resources, including routes
to output buffers.
•
Once CLK0 is Low, the multiplexer output stays Low
DS031-2 (v3.5) November 5, 2007
Product Specification
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