R
Virtex-II Platform FPGAs: Functional Description
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= NONE
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= FIXED
(PS/256) x PERIOD
(PS negative)
(PS/256) x PERIOD
(PS positive)
CLKIN
CLKIN
CLKIN
CLKFB
CLKOUT_PHASE_SHIFT
= VARIABLE
(PS/256) x PERIOD
(PS negative)
(PS/256) x PERIOD
CLKIN
CLKIN
DS031_48_101201
(PS positive)
Figure 46: Fine-Phase Shifting Effects
Table 22 lists fine-phase shifting control pins, when used in
variable mode.
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the PHASE_SHIFT value never changes after configu-
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Table 22: Fine-Phase Shifting Control Pins
Control Pin
PSINCDEC
PSEN
Direction
Function
in
in
Increment or decrement
Enable phase shift
Clock for phase shift
Active when completed
PSCLK
in
PSDONE
out
Taking both of these components into consideration, the fol-
lowing are some usage examples:
Two separate components of the phase shift range must be
understood:
•
•
•
If PERIOD
= 2 * FINE_SHIFT_RANGE, then
CLKIN
PHASE_SHIFT in fixed mode is limited to 128, and in
variable mode it is limited to 64.
•
•
PHASE_SHIFT attribute range
FINE_SHIFT_RANGE DCM timing parameter range
If PERIOD
= FINE_SHIFT_RANGE, then
CLKIN
PHASE_SHIFT in fixed mode is limited to 255, and in
variable mode it is limited to 128.
The PHASE_SHIFT attribute is the numerator in the following
equation:
If PERIOD
≤ 0.5 * FINE_SHIFT_RANGE, then
CLKIN
Phase Shift (ns) = (PHASE_SHIFT/256) * PERIOD
CLKIN
PHASE_SHIFT is limited to 255 in either mode.
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the FINE_SHIFT_RANGE component, which represents
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters in Module 3.
Operating Modes
The frequency ranges of DCM input and output clocks
depend on the operating mode specified, either
low-frequency mode or high-frequency mode, according to
Table 23. (For actual values, see Virtex-II Switching Charac-
teristics in Module 3). The CLK2X, CLK2X180, CLK90, and
CLK270 outputs are not available in high-frequency mode.
Absolute range (fixed mode) = FINE_SHIFT_RANGE
Absolute range (variable mode) = FINE_SHIFT_RANGE/2
High or low-frequency mode is selected by an attribute.
Table 23: DCM Frequency Ranges
Low-Frequency Mode
High-Frequency Mode
Output Clock
CLK0, CLK180
CLKIN Input
CLK Output
CLKIN Input
CLK Output
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF
CLK90, CLK270
CLK2X, CLK2X180
CLKDV
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF
NA
NA
NA
NA
CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF
CLKFX, CLKFX180
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF
CLKOUT_FREQ_FX_HF
DS031-2 (v3.5) November 5, 2007
Product Specification
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