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QPro Virtex 2.5V Radiation-Hardened FPGAs
DS028 (v2.1) November 5, 2010
Product Specification
Features
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0.22 µm 5-layer epitaxial process
QML certified
Radiation-hardened FPGAs for space and satellite
applications
Guaranteed total ionizing dose to 100K Rad(si)
Latch-up immune to LET = 125 MeV cm
2
/mg
SEU immunity achievable with recommended
redundancy implementation
Guaranteed over the full military temperature range
(–55°C to +125°C)
Fast, high-density Field-Programmable Gate Arrays
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Densities from 100k to 1M system gates
System performance up to 200 MHz
Hot-swappable for Compact PCI
16 high-performance interface standards
Connects directly to ZBTRAM devices
Four dedicated delay-locked loops (DLLs) for
advanced clock control
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensing device
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Supported by FPGA Foundation™ and Alliance
Development Systems
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Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Wide selection of PC and workstation platforms
Unlimited reprogrammability
Four programming modes
SRAM-based in-system configuration
Available to Standard Microcircuit Drawings. Contact
Defense Supply Center Columbus (DSCC) for more
information at
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5962-99572 for XQVR300
5962-99573 for XQVR600
5962-99574 for XQVR1000
Multi-standard SelectIO™ interfaces
Description
The QPro™ Virtex® family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22 µm CMOS process. These
advances make QPro Virtex FPGAs powerful and flexible
alternatives to mask-programmed gate arrays. The Virtex
radiation-hardened family comprises the three members
shown in
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design flexibility while reducing time-to-market.
Refer to the Virtex 2.5V FPGA commercial data sheet at
for
more information on device architecture and timing
specifications.
Built-in clock-management circuitry
Hierarchical memory system
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Flexible architecture that balances speed and density
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© Copyright 2001–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS028 (v2.1) November 5, 2010
Product Specification
1
XILINX [ XILINX, INC ]
