R
QPro Virtex 2.5V QML High-Reliability FPGAs
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Switching Characteristics Standard Adjustments" on page 8.
Speed Grade
-4
Symbol
Propagation Delays
TIOOP
Description
Min
Max
Units
O input to pad
-
-
3.5
4.0
ns
ns
TIOOLP
O input to pad via transparent latch
3-State Delays
TIOTHZ
T input to pad high-impedance(1)
-
-
-
-
-
2.4
3.7
3.0
4.2
6.3
ns
ns
ns
ns
ns
TIOTON
T input to valid data on pad
TIOTLPHZ
T input to pad high-impedance via transparent latch(1)
T input to valid data on pad via transparent latch
GTS to pad high-impedance(1)
TIOTLPON
TGTS
Sequential Delays
TIOCKP
Clock CLK to pad
-
-
-
3.5
2.9
4.1
ns
ns
TIOCKHZ
Clock CLK to pad high-impedance (synchronous)(1)
Clock CLK to valid data on pad (synchronous)
TIOCKON
ns
(2)
Setup and Hold Times before/after Clock CLK
TIOOCK/TIOCKO O input
Setup Time / Hold Time
1.3 / 0
1.0 / 0
1.4 / 0
0.9 / 0
1.1 / 0
1.3 / 0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
T
IOOCECK/TIOCKOCE OCE input
T
IOSRCKO/TIOCKOSR SR input (OFF)
T
IOTCK/TIOCKT
IOTCECK/TIOCKTCE
IOSRCKT/TIOCKTSR
3-state setup times, T input
T
T
3-state setup times, TCE input
3-state setup times, SR input (TFF)
Set/Reset Delays
TIOSRP
SR input to pad (asynchronous)
4.6
3.9
5.1
-
-
-
ns
ns
ns
TIOSRHZ
SR input to pad high-impedance (asynchronous)(1)
SR input to valid data on pad (asynchronous)
TIOSRON
Notes:
1. High-impedance turn-off delays should not be adjusted.
2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
www.xilinx.com
7
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
