R
XC3000 Series Field Programmable Gate Arrays
XC3000L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
Symbol
-8
Description
Min
Max
Units
Combinatorial Delay
Logic Variables
A, B, C, D, E, to outputs X or Y
FG Mode
1
8
T
6.7
7.5
ns
ns
ILO
F and FGM Mode
Sequential delay
Clock k to outputs X or Y
T
T
7.5
ns
CKO
QLO
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
14.0
14.8
ns
ns
F and FGM Mode
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG Mode
F and FGM Mode
DI
2
T
5.0
5.8
5.0
6.0
ns
ns
ns
ns
ICK
Data In
4
6
T
DICK
Enable Clock
EC
T
ECCK
Hold Time after clock K
Logic Variables
Data In
7
A, B, C, D, E
DI2
EC
3
5
7
T
0
2.0
2.0
ns
ns
ns
CKI
T
CKDI
T
CKEC
Enable Clock
Clock
Clock High time
Clock Low time
11
12
T
T
5.0
5.0
ns
ns
CH
CL
Max. flip-flop toggle rate
F
80.0
MHz
CLK
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
13
9
T
T
RIO
7.0
7.0
ns
ns
RPW
Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y
T
T
16.0
ns
ns
MRW
23.0
MRQ
Notes: 1. Timing is based on the XC3042L, for other devices see timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.
November 9, 1998 (Version 3.1)
7-49
XILINX [ XILINX, INC ]
