R
XC3000 Series Field Programmable Gate Arrays
XC3000L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000L Operating Conditions
Symbol
Description
Min
3.0
Max
Units
V
V
Supply voltage relative to GND Commercial 0°C to +85°C junction
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
Input signal transition time
3.6
CC
V
2.0
V
+0.3
CC
V
IH
V
-0.3
0.8
250
V
IL
T
ns
IN
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to
restrict operation to the 3.0 to 3.6 V range later, when smaller device geometries might preclude operation at 5V. Operating
conditions are guaranteed in the 3.0 – 3.6 V V
range.
CC
XC3000L DC Characteristics Over Operating Conditions
Symbol
Description
High-level output voltage (@ I = –4.0 mA, V min)
Min
Max
0.40
0.2
Units
V
V
2.40
OH
OH
CC
V
Low-level output voltage (@ I = 4.0 mA, V min)
V
OL
OL
CC
V
High-level output voltage (@ I = –4.0 mA, V min)
V
-0.2
V
OH
OH
CC
CC
7
V
Low-level output voltage (@ I = 4.0 mA, V min)
V
OL
OL
CC
V
Power-down supply voltage (PWRDWN must be Low)
2.30
V
CCPD
CCPD
I
Power-down supply current (V
@ T
)
10
µA
CC(MAX)
MAX
1
Quiescent FPGA supply current in addition to I
CCPD
I
CCO
Chip thresholds programmed as CMOS levels
20
µA
µA
I
Input Leakage Current
–10
+10
IL
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
pF
C
IN
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
15
20
pF
pF
I
Pad pull-up (when selected) @ V = 0 V3
0.01
0.17
2.50
mA
mA
RIN
IN
I
Horizontal Longline pull-up (when selected) @ logic Low
RLL
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a tie option. ICCO is in addition to ICCPD
.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC3090L.
3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up.
November 9, 1998 (Version 3.1)
7-47
XILINX [ XILINX, INC ]
