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5962-9561101MZC 参数 Datasheet PDF下载

5962-9561101MZC图片预览
型号: 5962-9561101MZC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 190MHz, 320-Cell, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164]
分类和应用: 可编程逻辑
文件页数/大小: 76 页 / 730 K
品牌: XILINX [ XILINX, INC ]
 浏览型号5962-9561101MZC的Datasheet PDF文件第42页浏览型号5962-9561101MZC的Datasheet PDF文件第43页浏览型号5962-9561101MZC的Datasheet PDF文件第44页浏览型号5962-9561101MZC的Datasheet PDF文件第45页浏览型号5962-9561101MZC的Datasheet PDF文件第47页浏览型号5962-9561101MZC的Datasheet PDF文件第48页浏览型号5962-9561101MZC的Datasheet PDF文件第49页浏览型号5962-9561101MZC的Datasheet PDF文件第50页  
R
XC3000 Series Field Programmable Gate Arrays  
XC3000L Absolute Maximum Ratings  
Symbol  
Description  
Supply voltage relative to GND  
Units  
V
V
–0.5 to +7.0  
–0.5 to V +0.5  
CC  
V
Input voltage with respect to GND  
Voltage applied to 3-state output  
Storage temperature (ambient)  
V
IN  
CC  
V
–0.5 to V +0.5  
V
TS  
CC  
T
T
–65 to +150  
+260  
°C  
°C  
°C  
°C  
STG  
SOL  
Maximum soldering temperature (10 s @ 1/16 in.)  
Junction temperature plastic  
+125  
T
J
Junction temperature ceramic  
+150  
Note:  
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are  
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under  
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended  
periods of time may affect device reliability.  
XC3000L Global Buffer Switching Characteristics Guidelines  
Speed Grade  
Symbol  
-8  
Description  
Max  
Units  
Global and Alternate Clock Distribution1  
Either: Normal IOB input pad through clock buffer  
to any CLB or IOB clock input  
Or: Fast (CMOS only) input pad through clock  
buffer to any CLB or IOB clock input  
T
9.0  
7.0  
ns  
ns  
PID  
T
PIDC  
TBUF driving a Horizontal Longline (L.L.)1  
I to L.L. while T is Low (buffer active)  
Tto L.L. active and valid with single pull-up resistor  
Tto L.L. High with single pull-up resistor  
T
5.0  
12.0  
24.0  
ns  
ns  
ns  
IO  
T
ON  
T
PUS  
BIDI  
Bidirectional buffer delay  
T
2.0  
ns  
BIDI  
Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator.  
2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.  
7-48  
November 9, 1998 (Version 3.1)  
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