R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Length Count Match
CCLK Period
CCLK
F
DONE
I/O
XC2000
Global Reset
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
F
DONE
I/O
XC3000
Heavy lines describe
default timing
Global Reset
F
DONE
I/O
C1
C2
C2
C3
C3
C4
XC4000E/X
CCLK_NOSYNC
C4
6
GSR Active
C2
C3
C4
DONE IN
F
DONE
I/O
C1, C2 or C3
Di
XC4000E/X
CCLK_SYNC
Di+1
Di+1
GSR Active
Di
F
DONE
I/O
C1
U2
U2
U3
U3
U4
XC4000E/X
UCLK_NOSYNC
U4
GSR Active
U2
U3
U4
DONE IN
F
DONE
I/O
C1
U2
XC4000E/X
UCLK_SYNC
Di
Di+1
Di+2
Di+2
GSR Active
Di Di+1
Synchronization
Uncertainty
UCLK Period
X9024
Figure 47: Start-up Timing
May 14, 1999 (Version 1.6)
6-53
XILINX [ XILINX, INC ]
