R
XC4000E and XC4000X Series Field Programmable Gate Arrays
used), and if RAM is present, the RAM content must be
unchanged.
V
No
Statistically, one error out of 2048 might go undetected.
CC
>3.5 V
Boundary Scan
Instructions
Available:
Configuration Sequence
Yes
There are four major steps in the XC4000 Series power-up
configuration sequence.
Test M0 Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
•
•
•
•
Configuration Memory Clear
Initialization
Configuration
Yes
Keep Clearing
Configuration Memory
Start-Up
The full process is illustrated in Figure 46.
EXTEST*
SAMPLE/PRELOAD
BYPASS
Completely Clear
Configuration Memory
Once More
Configuration Memory Clear
~1.3 µs per Frame
CONFIGURE*
(* if PROGRAM = High)
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec-
ommended, the longest delay takes precedence. There-
fore, devices with different time delays can easily be mixed
and matched in a daisy chain.
INIT
High? if
Master
No
Master Waits 50 to 250 µs
Before Sampling Mode Lines
Yes
Sample
Mode Lines
Master CCLK
Goes Active
Load One
Configuration
Data Frame
This delay is applied only on power-up. It is not applied
when re-configuring an FPGA by pulsing the PROGRAM
pin
Yes
Frame
Error
Pull INIT Low
and Stop
X2
X15
No
X16
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
SAMPLE/PRELOAD
Config-
uration
memory
Full
No
BYPASS
SERIAL DATA IN
Yes
Polynomial: X16 + X15 + X2 + 1
Pass
Configuration
Data to DOUT
1
1
1
1
1
0
15 14 13 12 11 10
9
8
7
6
5
LAST DATA FRAME
CRC – CHECKSUM
CCLK
Count Equals
Length
No
X1789
Readback Data Stream
Count
Yes
Figure 45: Circuit for Generating CRC-16
Start-Up
Sequence
F
Operational
EXTEST
SAMPLE PRELOAD
BYPASS
If Boundary Scan
is Selected
USER 1
USER 2
CONFIGURE
READBACK
X6076
Figure 46: Power-up Configuration Sequence
6-50
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
