R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 20: XC4000E Program Data
Device
XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E
Max Logic Gates
3,000
5,000
6,000
8,000
10,000
13,000
20,000
25,000
CLBs
100
196
256
324
400
576
784
1,024
(Row x Col.)
(10 x 10)
(14 x 14)
(16 x 16)
(18 x 18)
(20 x 20)
(24 x 24)
(28 x 28)
(32 x 32)
IOBs
80
360
112
616
128
768
144
936
160
1,120
226
192
1,536
266
224
2,016
256
2,560
Flip-Flops
Bits per Frame
Frames
126
166
186
206
306
346
428
572
644
716
788
932
1,076
1,220
Program Data
53,936
53,984
94,960
95,008
119,792
119,840
147,504
147,552
178,096
178,144
247,920
247,968
329,264
329,312
422,128
422,176
PROM Size
(bits)
Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
Table 21: XC4000EX/XL Program Data
Device
XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044
XC4052
XC4062
XC4085
6
Max Logic
Gates
2,000
5,000
10,000
13,000
20,000
28,000
36,000
44,000
52,000
62,000
85,000
CLBs
64
196
400
576
784
1,024
1,296
1,600
1,936
2,304
3,136
(Row x
Column)
(8 x 8)
(14 x 14) (20 x 20) (24 x 24) (28 x 28) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48) (56 x 56)
IOBs
64
112
616
205
160
1,120
277
192
1,536
325
224
2,016
373
256
2,560
421
288
3,168
469
320
3,840
517
352
4,576
565
384
5,376
613
448
7,168
709
Flip-Flops
256
133
Bits per
Frame
Frames
459
741
1,023
1,211
1,399
1,587
1,775
1,963
2,151
2,339
2,715
Program Data
61,052
61,104
151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940
151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992
PROM Size
(bits)
Notes: 1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detec-
During Readback, 11 bits of the 16-bit checksum are added
tion in data transmission applications. Generally, the trans-
to the end of the Readback data stream. The checksum is
mitting system performs a calculation on the serial
computed using the CRC-16 CCITT polynomial, as shown
bitstream. The result of this calculation is tagged onto the
in Figure 45. The checksum consists of the 11 most signif-
data stream as additional check bits. The receiving system
icant bits of the 16-bit code. A change in the checksum indi-
performs an identical calculation on the bitstream and com-
cates a change in the Readback bitstream. A comparison
pares the result with the received checksum.
to a previous checksum is meaningful only if the readback
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 19. If a frame data
error is detected during the loading of the FPGA, the con-
data is independent of the current device state. CLB out-
puts should not be included (Read Capture option not
May 14, 1999 (Version 1.6)
6-49
XILINX [ XILINX, INC ]
