IOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(slew-rate limited)
Symbol
-70
Min
Max
-100
Min Max
-125
Min Max
Units
3
4
T
PID
T
PTG
T
IKRI
6
21
5.5
4
17
4
3
16
3
ns
ns
ns
1
T
PICK
20
17
16
ns
7
7
10
10
9
9
8
8
T
OKPO
T
OKPO
T
OPF
T
OPS
T
TSHZ
T
TSHZ
T
TSON
T
TSON
13
33
9
29
8
28
14
34
10
27
6
23
8
25
12
29
9
24
5
20
7
24
11
27
ns
ns
ns
ns
ns
ns
ns
ns
5
6
T
OOK
T
OKO
10
0
9
0
8
0
ns
ns
11
12
T
IOH
T
IOL
F
CLK
5
5
70
4
4
100
3
3
125
ns
ns
MHz
13
15
15
T
RRI
T
RPO
T
RPO
25
35
53
24
33
45
23
29
42
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad setup time and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but the subtracted value cannot be
less than zero (i.e., negative hold time). Negative hold time means that the delay in the input data is adequate for the
external system hold time
to be zero, provided the input clock uses the Global signal distribution from pad to IK .
2-159
XILINX [ XILINX, INC ]
