CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
Set-up time before clock K
Logic Variables
A, B, C, D, E
Data In
DI
Enable Clock
EC
Reset Direct inactive RD
Hold Time after clock K
Logic Variables
Data In
Enable Clock
Symbol
-70
Min Max
-100
Min
Max
-125
Min
Max Units
1 T
ILO
9.0
7.0
5.5
ns
8 T
CKO
T
QLO
6.0
13.0
5.0
10.0
4.5
8.0
ns
ns
2 T
ICK
4 T
DICK
6 T
ECCK
8.0
5.0
7.0
1.0
7.0
4.0
5.0
1.0
5.5
3.0
4.5
1.0
ns
ns
ns
ns
A, B, C, D, E
DI
EC
3 T
CKI
5 T
CKDI
7 T
CKEC
0
4.0
0
0
2.0
0
0
1.5
0
ns
ns
ns
Clock
Clock High time
Clock Low time
Max flip-flop toggle rate
Reset Direct (RD)
RD width
delay from rd to outputs X or Y
Global Reset (RESET Pad)*
RESET width (Low)
delay from RESET pad to outputs X or Y
11 T
CH
12 T
CL
F
CLK
5.0
5.0
70
4.0
4.0
100
3.0
3.0
125
ns
ns
MHz
13 T
RPW
9 T
RIO
8.0
8.0
7.0
7.0
6.0
6.0
ns
ns
T
MRW
T
MRQ
25.0
23.0
21.0
19.0
20.0
17.0
ns
ns
*Timing is based on the XC3042, for other devices see XACT timing calculator.
Note: The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
2-157
XILINX [ XILINX, INC ]
