XC3000 Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y)
(Combinatorial)
1 T
ILO
CLB Input
(A,B,C,D,E)
2 T
ICK
CLB Clock
12 T
CL
4 T
DICK
CLB Input
(Direct In)
6 T
ECCK
CLB Input
(Enable Clock)
8 T
CKO
CLB Output
(Flip-Flop)
7 T
CKEC
11 T
CH
5 T
CKDI
3 T
CKI
CLB Input
(Reset Direct)
13 T
RPW
9 T
RIO
CLB Output
(Flip-Flop)
X5388
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
Description
Global and Alternate Clock Distribution*
Either:
Normal
IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast
(CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF
driving a Horizontal Longline (L.L.)*
I to L.L. while T is Low (buffer active)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
BIDI
Bidirectional buffer delay
Symbol
-70
Max
-100
Max
-125
Max
Units
T
PID
T
PIDC
8.0
6.5
7.5
6.0
7.0
5.7
ns
ns
T
IO
T
ON
T
ON
T
PUS
T
PUF
5.0
11.0
12.0
24.0
17.0
4.7
10.0
11.0
22.0
15.0
4.5
9.0
10.0
17.0
12.0
ns
ns
ns
ns
ns
T
BIDI
2.0
1.8
1.7
ns
* Timing is based on the XC3042, for other devices see XACT timing calculator.
2-156
XILINX [ XILINX, INC ]
