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X4003M8I 参数 Datasheet PDF下载

X4003M8I图片预览
型号: X4003M8I
PDF下载: 下载PDF文件 查看货源
内容描述: CPU监控器 [CPU Supervisor]
分类和应用: 光电二极管监控
文件页数/大小: 18 页 / 380 K
品牌: XICOR [ XICOR INC. ]
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X4003/X4005  
PIN CONFIGURATION  
8-Pin JEDEC SOIC, MSOP  
V
1
2
3
4
8
7
6
5
NC  
NC  
CC  
WP  
SCL  
SDA  
RESET  
V
SS  
PIN DESCRIPTION  
Pin  
Pin  
Pin  
(SOIC/DIP)  
TSSOP  
(MSOP)  
Name  
NC  
Function  
1
2
3
3
4
5
No internal connections  
No internal connections  
NC  
2
RESET/  
RESET  
Reset Output. RESET/RESET is an active LOW/HIGH, open  
drain output which goes active whenever V falls below the  
minimum V sense level. It will remain active until V rises  
above the minimum V sense level for 250ms. RESET/  
CC  
CC  
CC  
CC  
RESET goes active if the watchdog timer is enabled and SDA  
remains either HIGH or LOW longer than the selectable  
Watchdog time out period. A falling edge of SDA, while SCL  
also toggles from HIGH to LOW followed by a stop condition  
resets the watchdog timer. RESET/RESET goes active on  
power up and remains active for 250ms after the power supply  
stabilizes.  
4
5
6
7
3
4
V
Ground  
SS  
SDA  
Serial Data. SDA is a bidirectional pin used to transfer data  
into and out of the device. It has an open drain output and may  
be wire ORed with other open drain or open collector outputs.  
This pin requires a pull up resistor and the input buffer is  
always active (not gated).  
Watchdog Input. A HIGH to LOW transition on the SDA while  
SCL also toggles from HIGH to LOW follow by a stop condition  
resets the watchdog timer. The absence of this procedure with-  
in the watchdog time out period results in RESET/RESET going  
active.  
6
7
8
8
1
2
5
6
1
SCL  
WP  
Serial Clock. The serial clock controls the serial bus timing for  
data input and output.  
Write Protect. WP HIGH prevents changes to the watchdog timer  
setting.  
V
Supply voltage  
CC  
Characteristics subject to change without notice. 2 of 18  
REV 1.1.3 4/30/02  
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