X28HC64
64K
X28HC64
5 Volt, Byte Alterable E
2
PROM
•
•
8K x 8 Bit
FEATURES
•
•
•
•
•
•
55ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS
—40 mA Active Current Max.
—200
µ
A Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32
µ
s Typical
Software Data Protection
End of Write Detection
—DATA Polling
—Toggle Bit
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28HC64 is an 8K x 8 E
2
PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28HC64 is a 5V only device. The
X28HC64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and en-
abling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features
DATA
Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
TSOP
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A12
NC
NC
VCC
NC
WE
NC
A8
A9
A11
OE
PIN CONFIGURATIONS
VCC
WE
A7
A12
NC
NC
NC
PLASTIC DIP
FLAT PACK
CERDIP
SOIC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28HC64
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
LCC
PLCC
X28HC64
4
3
2
1 32 31 30
29
28
27
26
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
X28HC64
25
24
23
22
PGA
I/O1
I/O2
I/O3
I/O5
I/O6
12
13
15
17
18
I/O0
A0
11
10
A1
A3
A5
A2
8
A4
6
A12
2
A7
3
X28HC64
VSS
I/O4
I/O7
14
16
19
CE
20
OE
22
A10
21
A11
23
A8
25
NC
26
3857 ILL F22
10
11
12
21
13
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
9
7
3857 FHD F03
5
3857 FHD F02.1
VCC
A9
28
24
NC
1
WE
27
4
A6
3857 FHD F04
BOTTOM VIEW
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3857-3.0 8/5/97 T1/C0/D0 EW
1
Characteristics subject to change without notice
XICOR [ XICOR INC. ]
