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X28C256D 参数 Datasheet PDF下载

X28C256D图片预览
型号: X28C256D
PDF下载: 下载PDF文件 查看货源
内容描述: 5伏,可变的字节E2PROM [5 Volt, Byte Alterable E2PROM]
分类和应用: 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 24 页 / 114 K
品牌: XICOR [ XICOR INC. ]
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X28C256  
DEVICE OPERATION  
Read  
Write Operation Status Bits  
The X28C256 provides the user two write operation  
status bits. These can be used to optimize a system  
write cycle time. The status bits are mapped onto the  
I/O bus as shown in Figure 1.  
Read operations are initiated by both OE and CE LOW.  
The read operation is terminated by either CE or OE  
returning HIGH. This two line control architecture elimi-  
natesbuscontentioninasystemenvironment. Thedata  
bus will be in a high impedance state when either OE or  
CE is HIGH.  
Figure 1. Status Bit Assignment  
Write  
I/O DP TB  
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4
3
2
1
0
Write operations are initiated when bothCE and WE are  
LOWandOEisHIGH.TheX28C256supportsbothaCE  
and WE controlled write cycle. That is, the address is  
latchedbythefallingedgeofeitherCEorWE,whichever  
occurslast. Similarly, thedataislatchedinternallybythe  
rising edge of either CE or WE, whichever occurs first.  
A byte write operation, once initiated, will automatically  
continue to completion, typically within 5ms.  
RESERVED  
TOGGLE BIT  
DATA POLLING  
3855 FHD F11  
DATA Polling (I/O )  
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The X28C256 features DATA Polling as a method to  
indicate to the host system that the byte write or page  
writecyclehascompleted.DATAPollingallowsasimple  
bittestoperationtodeterminethestatusoftheX28C256,  
eliminating additional interrupt inputs or external hard-  
ware. During the internal programming cycle, any at-  
tempt to read the last byte written will produce the  
Page Write Operation  
The page write feature of the X28C256 allows the entire  
memory to be written in 2.5 seconds. Page write allows  
twotosixty-fourbytesofdatatobeconsecutivelywritten  
to the X28C256 prior to the commencement of the  
internal programming cycle. The host can fetch data  
from another device within the system during a page  
write operation (change the source address), but the  
complement of that data on I/O (i.e. write data = 0xxx  
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xxxx, read data = 1xxx xxxx). Once the programming  
cycle is complete, I/O will reflect true data. Note: If the  
X28C256 is in the protected state and an illegal write  
operation is attempted DATA Polling will not operate.  
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page address (A through A ) for each subsequent  
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valid write cycle to the part during this operation must be  
the same as the initial page address.  
Toggle Bit (I/O )  
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The page write mode can be initiated during any write  
operation. Following the initial byte write cycle, the host  
can write an additional one to sixty-three bytes in the  
samemannerasthefirstbytewaswritten. Eachsucces-  
sive byte load cycle, started by the WE HIGH to LOW  
transition, must begin within 100µs of the falling edge of  
the preceding WE. If a subsequent WE HIGH to LOW  
transition is not detected within 100µs, the internal  
automatic programming cycle will commence. There is  
no page write window limitation. Effectively the page  
write window is infinitely wide, so long as the host  
continuestoaccessthedevicewithinthebyteloadcycle  
time of 100µs.  
The X28C256 also provides another method for deter-  
mining when the internal write cycle is complete. During  
the internal programming cycle I/O will toggle from  
HIGH to LOW and LOW to HIGH on subsequent  
attempts to read the device. When the internal cycle is  
complete the toggling will cease and the device will be  
accessible for additional read or write operations.  
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