X28C256
PIN DESCRIPTIONS
PIN NAMES
Symbol
A –A
Addresses (A –A )
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
14
The Address inputs select an 8-bit memory location
during a read or write operation.
0
14
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
V
CC
V
SS
Ground
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
3855 PGM T01
PIN CONFIGURATION
Data In/Data Out (I/O –I/O )
0
7
PGA
Data is written to or read from the X28C256 through the
I/O pins.
I/O
12
I/O
13
I/O
3
15
I/O
17
I/O
18
1
2
5
6
I/O
11
A
10
V
14
I/O
16
I/O
19
0
0
SS
4
7
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C256.
A
A
A
A
CE
20
A
21
1
3
2
4
10
11
9
7
8
6
X28C256
OE
22
A
23
A
A
V
28
A
24
A
25
5
6
12
7
CC
9
8
5
4
2
3
A
A
A
WE
27
A
13
26
14
1
3855 FHD F04
BOTTOM VIEW
FUNCTIONAL DIAGRAM
256K-BIT
E PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
2
A –A
0
14
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
OE
WE
CONTROL
LOGIC AND
TIMING
V
CC
V
SS
3855 FHD F01
2
XICOR [ XICOR INC. ]
