X25128
Write-Protect Enable
indefinitely. The read operation is terminated by taking
CS high. Refer to the read E PROM array operation
sequence illustrated in Figure 1.
2
The Write-Protect-Enable (WPEN) is available for the
X25128 as a nonvolatile enable bit for the WP pin.
To read the status register the CS line is first pulled
low to select the device followed by the 8-bit instruc-
tion. After the RDSR opcode is sent, the contents of
the status register are shifted out on the SO line. The
read status register sequence is illustrated in Figure 2.
Protected Unprotected Status
WPEN WP WEL Blocks
Blocks
Protected Protected Protected
Protected Writable Writable
Protected Protected Protected
Protected Writable Protected
Protected Protected Protected
Register
0
0
1
1
X
X
X
0
1
0
1
0
1
X
Low
Low
High
High
Write Sequence
Prior to any attempt to write data into the X25128, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken low,
then the WREN instruction is clocked into the X25128.
After all eight bits of the instruction are transmitted, CS
must then be taken high. If the user continues the write
operation without taking CS high after issuing the
WREN instruction, the write operation will be ignored.
Protected
Writable
Writable
3091 PGM T05.1
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when
WP pin is low, and the WPEN bit is “1”. Hardware write
protection is disabled when either the WP pin is high
or the WPEN bit is “0”. When the chip is hardware
write protected, nonvolatile writes are disabled to the
Status Register, including the Block Protect bits and
the WPEN bit itself, as well as the block-protected
sections in the memory array. Only the sections of the
memory array that are not block-protected can be
written.
2
To write data to the E PROM memory array, the user
issues the write instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go low and remain
low for the duration of the operation. The host may
continue to write up to 32 bytes of data to the X25128.
The only restriction is the 32 bytes must reside on the
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
Note: Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the WP pin is held low.
For the write operation (byte or page write) to be
completed, CS can only be brought high after bit 0 of
data byte N is clocked in. If it is brought high at any
other time the write operation will not be completed.
Refer to Figures 4 and 5 below for a detailed illustra-
tion of the write sequences and time frames in which
CS going high are valid.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
2
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”.This sequence is shown in Figure 6.
When reading from the E PROM array, CS is first
pulled low to select the device. The 8-bit read instruc-
tion is transmitted to the X25128, followed by the
16-bit address of which the last 14 are used. After the
read opcode and address are sent, the data stored in
the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next
address can be read sequentially by continuing to
provide clock pulses. The address is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached ($3FFF) the address counter rolls over to
address $0000 allowing the read cycle to be continued
While the write is in progress, following a status
2
register or E PROM write sequence, the status
register may be read to check the WIP bit. During this
time the WIP bit will be high.
Hold Operation
The HOLD input should be high (at V ) under normal
IH
operation. If a data transfer is to be interrupted HOLD
can be pulled low to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
4
XICOR [ XICOR INC. ]
