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X25128S 参数 Datasheet PDF下载

X25128S图片预览
型号: X25128S
PDF下载: 下载PDF文件 查看货源
内容描述: SPI串行ê 2 PROM带座锁TM保护 [SPI Serial E 2 PROM with Block Lock TM Protection]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 15 页 / 80 K
品牌: XICOR [ XICOR INC. ]
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X25128  
PIN DESCRIPTIONS  
Serial Output (SO)  
low. If the pause feature is not used, HOLD should be  
held high at all times.  
SO is a push/pull serial data output pin. During a read  
cycle, data is shifted out on this pin. Data is clocked  
out by the falling edge of the serial clock.  
PIN CONFIGURATION  
Not to scale  
14 Lead SOIC  
Serial Input (SI)  
1
2
CS  
SO  
14  
13  
V
CC  
SI is the serial data input pin. All opcodes, byte  
addresses, and data to be written to the memory are  
input on this pin. Data is latched by the rising edge of  
the serial clock.  
HOLD  
NC  
12  
11  
10  
9
NC  
3
4
NC  
NC  
NC  
WP  
.344”  
X24128  
NC  
5
6
7
SCK  
SI  
Serial Clock (SCK)  
V
8
SS  
The Serial Clock controls the serial bus timing for data  
input and output. Opcodes, addresses, or data present  
on the SI pin are latched on the rising edge of the  
clock input, while data on the SO pin change after the  
falling edge of the clock input.  
.244”  
16 Lead SOIC  
1
2
16  
CS  
SO  
V
CC  
15  
14  
13  
12  
11  
HOLD  
Chip Select (CS)  
NC  
NC  
3
4
When CS is high, the X25128 is deselected and the  
SO output pin is at high impedance and unless an  
internal write operation is underway, the X25128 will  
be in the standby power mode. CS low enables the  
X25128, placing it in the active power mode. It should  
be noted that after power-up, a high to low transition  
on CS is required prior to the start of any operation.  
NC  
NC  
NC  
NC  
WP  
.394”  
X25128  
NC  
5
6
7
8
NC  
SCK  
SI  
10  
9
V
SS  
.244”  
Write Protect (WP)  
8 Lead PDIP  
When WP is low and the nonvolatile bit WPEN is “1”,  
nonvolatile writes to the X25128 status register are  
disabled, but the part otherwise functions normally.  
When WP is held high, all functions, including nonvola-  
tile writes operate normally. WP going low while CS is  
still low will interrupt a write to the X25128 status  
register. If the internal write cycle has already been  
initiated, WP going low will have no effect on a write.  
1
2
8
CS  
SO  
V
CC  
7
6
5
HOLD  
SCK  
SI  
.430”  
X25128  
WP  
3
4
V
SS  
.325”  
3091 FM 02  
PIN NAMES  
The WP pin function is blocked when the WPEN bit in  
the status register is “0”. This allows the user to install  
the X25128 in a system with WP pin grounded and still  
be able to write to the status register.The WP pin func-  
tions will be enabled when the WPEN bit is set “0”.  
Symbol  
Description  
Chip Select Input  
Serial Output  
Serial Input  
CS  
SO  
SI  
Hold (HOLD)  
SCK  
WP  
VSS  
VCC  
HOLD  
NC  
Serial Clock Input  
Write Protect Input  
Ground  
HOLD is used in conjunction with the CS pin to select  
the device. Once the part is selected and a serial  
sequence is underway, HOLD may be used to pause  
the serial communication with the controller without  
resetting the serial sequence. To pause, HOLD must  
be brought low while SCK is Low. To resume commu-  
nication, HOLD is brought high, again while SCK is  
Supply Voltage  
Hold Input  
No Connect  
3091 FM T01  
2