欢迎访问ic37.com |
会员登录 免费注册
发布采购

X25057M-2.7 参数 Datasheet PDF下载

X25057M-2.7图片预览
型号: X25057M-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 5MHz的低功耗SPI串行è 2 PROM与IDLock⑩记忆 [5MHz Low Power SPI Serial E 2 PROM with IDLock⑩ Memory]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 16 页 / 76 K
品牌: XICOR [ XICOR INC. ]
 浏览型号X25057M-2.7的Datasheet PDF文件第1页浏览型号X25057M-2.7的Datasheet PDF文件第3页浏览型号X25057M-2.7的Datasheet PDF文件第4页浏览型号X25057M-2.7的Datasheet PDF文件第5页浏览型号X25057M-2.7的Datasheet PDF文件第6页浏览型号X25057M-2.7的Datasheet PDF文件第7页浏览型号X25057M-2.7的Datasheet PDF文件第8页浏览型号X25057M-2.7的Datasheet PDF文件第9页  
X25057  
PIN DESCRIPTIONS  
Serial Output (SO)  
PIN CONFIGURATION  
Not to scale  
8 Lead SOIC/PDIP  
SO is a push/pull serial data output pin. During a read  
cycle, data is shifted out on this pin. Data is clocked out  
by the falling edge of the serial clock.  
V
CS  
SO  
WP  
1
2
3
4
8
7
6
5
CC  
Serial Input (SI)  
NC  
SCK  
SI  
*0.197"  
X25057  
SI is a serial data input pin. All opcodes, byte addresses,  
and data to be written to the memory are input on this  
pin. Data is latched by the rising edge of the serial clock.  
V
SS  
7033 FRM F02  
*0.244"  
Serial Clock (SCK)  
The Serial Clock controls the serial bus timing for data  
input and output. Opcodes, addresses, or data present  
on the SI pin are latched on the rising edge of the clock  
input, while data on the SO pin change after the falling  
edge of the clock input.  
8 Lead MSOP  
V
SO  
CS  
1
2
8
7
6
5
CC  
NC  
SI  
0.120"  
X25057  
V
3
SS  
SCK  
WP  
4
Chip Select (CS)  
7033 FRM F02.1  
When CS is HIGH, the X25057 is deselected and the SO  
output pin is at high impedance and unless an internal  
write operation is underway, the X25057 will be in the  
standby power mode. CS LOW enables the X25057,  
placing it in the active power mode. It should be noted  
that after power-up, a HIGH to LOW transition on CS is  
required prior to the start of any operation.  
0.193"  
8 Lead TSSOP  
NC  
SCK  
1
2
3
4
8
V
SI  
V
7
6
5
CC  
CS  
0.122"  
X25057  
SS  
Write Protect (WP)  
WP  
SO  
7033 FRM F02.2  
When WP is LOW, nonvolatile writes to the X25057 are  
disabled, but the part otherwise functions normally.When  
WP is held HIGH, all functions, including nonvolatile  
writes operate normally. WP going LOW while CS is still  
LOW will interrupt a write to the X25057. If the internal  
write cycle has already been initiated, WP going low will  
have no affect on this write.  
0.252"  
*SOIC Measurement  
PRINCIPLES OF OPERATION  
PIN NAMES  
The X25057 is a 512 x 8 E2PROM designed to interface  
directly with the synchronous Serial Peripheral Interface  
(SPI) of many popular microcontroller families.  
Symbol  
Description  
Chip Select Input  
CS  
SO  
SI  
The X25057 contains an 8-bit instruction register. It is  
accessed via the SI input, with data being clocked in on  
the rising edge of SCK. CS must be LOW and the WP  
input must be HIGH during the entire operation. Table 1  
contains a list of the instructions and their opcodes. All  
instructions, addresses and data are transferred MSB first.  
Serial Output  
Serial Input  
SCK  
WP  
Serial Clock Input  
Write Protect Input  
Ground  
V
V
SS  
Data input is sampled on the first rising edge of SCK  
after CS goes LOW. SCK is static, allowing the user to  
stop the clock and then start it again to resume opera-  
tions where left off.  
Supply Voltage  
No Connect  
CC  
NC  
7033 FRM T01  
2