Preliminary Information
X1288
Watchdog Timer Restart
V
THRESHOLD RESET PROCEDURE [Optional]
CC
The Watchdog Timer is started by a falling edge of
SDA when the SCL line is high and followed by a stop
bit. The start signal restarts the watchdog timer
counter, resetting the period of the counter back to the
maximum. If another start fails to be detected prior to
the watchdog timer expiration, then the RESET pin
becomes active. In the event that the start signal
occurs during a reset time out period, the start will
have no effect. When using a single START to refresh
watchdog timer, a STOP bit should be followed to reset
the device back to stand-by mode.
The X1288 is shipped with a standard V
threshold
CC
(V
) voltage. This value will not change over normal
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
TRIP
higher precision is needed in the V
value, the
TRIP
X1288 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile write control signal.
Setting the V
Voltage
TRIP
It is necessary to reset the trip point before setting the
new value.
LOW VOLTAGE RESET OPERATION
To set the new V
threshold voltage to the V pin and tie the RESET pin
to the programming voltage V . Then write data 00h to
address 01h. The stop bit following a valid write opera-
voltage, apply the desired V
TRIP
TRIP
When a power failure occurs, and the voltage to the
CC
part drops below a fixed v
voltage, a reset pulse is
TRIP
P
issued to the host microcontroller. The circuitry moni-
tors the V line with a voltage comparator which
CC
tion initiates the V
programming sequence. Bring
TRIP
senses a preset threshold voltage. Power up and
power down waveforms are shown in Figure 5. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
RESET to V
to complete the operation. Note: this
CC
operation may take up to 10 milliseconds to complete
and also writes 00h to address 01h of the EEPROM
array.
When the low voltage reset signal is active, the opera-
tion of any in progress nonvolatile write cycle is unaf-
fected, allowing a nonvolatile write to continue as long
as possible (down to the power on reset voltage). The
low voltage reset signal, when active, terminates in
progress communications to the device and prevents
new commands, to reduce the likelihood of data cor-
ruption.
Resetting the V
Voltage
TRIP
This procedure is used to set the V
voltage level. For example, if the current V
to a “native”
TRIP
is 4.4V
TRIP
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
be reset. When V
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
is reset, the new V
is some-
TRIP
TRIP
Figure 4. Watchdog Restart/Time Out
t
t
>t
RSP
RSP WDO
t
t
>t
t
RST
t
<t
RST
RSP WDO
RSP WDO
SCL
SDA
RESET
Stop
Start
Start
Note: All inputs are ignored during the active reset period (t
).
RST
17 of 31
REV 1.1.30 3/24/04
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