X1228
DESCRIPTION
PIN DESCRIPTIONS
X1228
14-Pin TSSOP/SOIC
The X1228 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
V
V
1
2
3
4
5
6
7
X1
X2
14
13
12
11
10
9
CC
BACK
PHZ/IRQ
NC
NC
NC
NC
RESET
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
NC
SCL
SDA
8
V
SS
NC = No internal connection
Serial Clock (SCL)
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar
has separate registers for Date, Month, Year and Day-
of-week. The calendar is correct through 2099, with
automatic leap year correction.
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs.The input buffer is always active (not gated).
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speeds.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.
The X1228 device integrates CPU Supervisor func-
tions and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from
power on. It will also assert RESET when Vcc goes
V
BACK
This input provides a backup supply voltage to the
device. V
event the V
supplies power to the device in the
supply fails. This pin can be connected
BACK
below the specified threshold. The V
threshold is
trip
CC
user repro-grammable. There is a WatchDog Timer
(WDT) with 3 selectable time-out periods (0.25s,
0.75s, 1.75s) and a disabled setting. The watchdog
activates the RESET pin when it expires.
to a battery, a Supercap or tied to ground if not used.
RESET Output – RESET
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
The device offers a backup power input pin. This
that the voltage has dropped below a fixed V
thresh-
TRIP
V
pin allows the device to be backed up by battery
BACK
old. It is an open drain active LOW output. Recom-
mended value for the pullup resistor is 5K Ohms. If
unused, tie to ground.
or SuperCap. The entire X1228 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1228 device remains fully operational
down to 1.8 volts (Standby Mode).
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is a CMOS output.
The X1228 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control.The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
When used as frequency output, this signal has a fre-
quency of 32.768kHz, 4096Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
Characteristics subject to change without notice. 9 of 31
REV 1.3 3/24/04
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XICOR [ XICOR INC. ]
