X1202
Table 3. Watchdog Timer Time Out Options
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
WD1 WD0
Watchdog Time Out Period
1.75 seconds
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
0
0
1
1
0
1
0
1
750 milliseconds
250 milliseconds
disabled
When V
exceeds the device V
threshold value
CC
TRIP
for 250ms the circuit releases RESET, allowing the
system to begin operation.
WATCHDOG TIMER OPERATION
WRITING TO THE CLOCK/CONTROL REGISTERS
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the watchdog timer
is set to off, the watchdog circuit is configured for low
power operation.
Changing any of the nonvolatile bits of the clock/control
register requires the following steps:
– Write a 02H to the status register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Watchdog Timer Restart
– Write a 06H to the status register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
The Watchdog Timer is restarted by a falling edge of
SDA when the SCL line is high. This is also referred to
as start condition.The restart signal restarts the watch-
dog timer counter, resetting the period of the counter
back to the maximum. If another start fails to be
detected prior to the watchdog timer expiration, then
the RESET pin becomes active. In the event that the
restart signal occurs during a reset time out period, the
restart will have no effect.
– Write one to 8 bytes to the clock/control registers with
the desired clock, alarm, or control data.This sequence
starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect.The RWEL bit is reset
by the completion of a nonvolatile write cycle, so the
sequence must be repeated to again initiate another
change to the CCR contents. If the sequence is not
completed for any reason (by sending an incorrect
number of bits or sending a start instead of a stop, for
example) the RWEL bit is not reset and the device
remains in an active mode.
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the part
drops below a fixed V
voltage, a reset pulse is
TRIP
issued to the host microcontroller. The circuitry monitors
the V line with a voltage comparator which senses a
CC
preset threshold voltage. Power up and power down
waveforms are shown in Figure 4. The low voltage reset
circuit is to be designed so the RESET signal is valid
down to 1.0V.
When the low voltage reset signal is active, the operation
of any in-progress nonvolatile write cycle is unaffected,
allowing a nonvolatile write to continue as long as possi-
ble (down to the power on reset voltage). The low voltage
reset signal, when active, terminates in-progress commu-
nications to the device and prevents new commands, to
reduce the likelihood of data corruption.
– The RWEL and WEL bits can be reset by writing a 0
to the status register.
– A read operation occurring between any of the previous
operations will not interrupt the register write operation.
POWER ON RESET
Application of power to the X1202 activates a power on
reset circuit that pulls the RESET pin active.This signal
provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
Characteristics subject to change without notice. 6 of 23
REV 1.1.8 5/17/01
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