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X1202V8-4.5A 参数 Datasheet PDF下载

X1202V8-4.5A图片预览
型号: X1202V8-4.5A
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO8, PLASTIC, TSSOP-8]
分类和应用: 时钟光电二极管外围集成电路
文件页数/大小: 23 页 / 173 K
品牌: XICOR [ XICOR INC. ]
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X1202  
Clock/Calendar Register (YR, MO, DT, HR, MN, SC)  
Note: Only the AL bits that are set when an SR read  
starts will be reset. An alarm bit that is set by an alarm  
occurring during an SR read operation will remain set  
after the read operation is complete.  
These registers depict BCD representations of the  
time. As such, SC (Seconds) and MN (Minutes) range  
from 0 to 59, HR (Hour) is 1 to 12 with an AM or PM  
indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date)  
is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.  
RWEL: Register Write Enable Latch—Volatile  
This bit is a volatile latch that powers up in the LOW  
(disabled) state. The RWEL bit must be set to “1” prior  
to any writes to the Clock/Control Registers. Writes to  
RWEL bit do not cause a nonvolatile write cycle, so the  
device is ready for the next operation immediately after  
the stop condition. A write to the CCR requires both  
the RWEL and WEL bits to be set in a specific  
sequence. RWEL bit is reset after each high voltage or  
reset by sending 00h to status register.  
24 Hour Time  
If the MIL bit of the HR register is 1, the RTC uses a  
24-hour format. If the MIL bit is 0, the RTC uses a 12-  
hour format and bit H21 functions as an AM/PM indica-  
tor with a ‘1’ representing PM. The clock defaults to  
Standard Time with H21 = 0.  
Leap Years  
Leap years add the day February 29 and are defined  
as those years that are divisible by 4.Years divisible by  
100 are not leap years, unless they are also divisible  
by 400. This means that the year 2000 is a leap year,  
the year 2100 is not. The X1202 does not correct for  
the leap year in the year 2100.  
WEL: Write Enable Latch—Volatile  
The WEL bit controls the access to the CCR and mem-  
ory array during a write operation. This bit is a volatile  
latch that powers up in the LOW (disabled) state. While  
the WEL bit is LOW, writes to the CCR or any array  
address will be ignored (no acknowledge will be issued  
after the Data Byte). The WEL bit is set by writing a “1”  
to the WEL bit and zeroes to the other bits of the Status  
Register. Once set, WEL remains set until either reset  
to “0” (by writing a “0” to the WEL bit and zeroes to the  
other bits of the Status Register) or until the part pow-  
ers up again. Writes to WEL bit do not cause a nonvol-  
atile write cycle, so the device is ready for the next  
operation immediately after the stop condition.  
STATUS REGISTER (SR)  
The Status Register is located in the RTC area at  
address 003Fh. This is a volatile register only and is  
used to control the WEL and RWEL write enable  
latches, read two power status and two alarm bits. This  
register is separate from both the array and the Clock/  
Control Registers (CCR).  
RTCF: Real Time Clock Fail Bit—Volatile  
Table 2. Status Register (SR)  
This bit is set to a ‘1’ after a total power failure. This is a  
read only bit that is set by hardware when the device  
powers up after having lost all power to the device. The  
Addr  
003Fh BAT AL1 AL0  
Default  
7
6
5
4
3
2
1
0
0
0
0
0
RWEL WEL RTCF  
bit is set regardless of whether V  
or V  
is  
0
0
0
0
0
1
CC  
BACK  
applied first. The loss of one or the other supplies does  
not result in setting the RTCF bit. The first valid write to  
the RTC (writing one byte is sufficient) resets the  
RTCF bit to ‘0’.  
BAT: Battery Supply—Volatile  
This bit set to “1” indicates that the device is operating  
from V , not V . It is a read only bit and is set/  
BACK  
CC  
reset by hardware.  
Unused Bits  
These devices do not use bits 3 or 4, but must have a  
zero in these bit positions. The Data Byte output during  
a SR read will contain zeros in these bit locations.  
AL1, AL0: Alarm bits—Volatile  
These bits announce if either alarm 1 or alarm 2 match  
the real time clock. If there is a match, the respective  
bit is set to ‘1’. The falling edge of the last data bit in a  
SR Read operation resets the flags.  
CONTROL REGISTER  
Watchdog Timer Control Bits  
The bits WD1 and WD0 control the period of the  
Watchdog Timer. See Table 3 for options.  
Characteristics subject to change without notice. 5 of 23  
REV 1.1.8 5/17/01  
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