Production Data
WM9715L
INTERFACE TIMING
Test Characteristics:
DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25°C to +85°C, unless otherwise stated.
CLOCK SPECIFICATIONS
tCLK_HIGH
tCLK_LOW
BITCLK
SYNC
tCLK_PERIOD
tSYNC_HIGH
tSYNC_LOW
tSYNC_PERIOD
Figure 17 Clock Specifications (50pF External Load)
PARAMETER
BITCLK frequency
SYMBOL
MIN
TYP
12.288
81.4
MAX
UNIT
MHz
ns
BITCLK period
tCLK_PERIOD
BITCLK output jitter
BITCLK high pulse width (Note 1)
BITCLK low pulse width (Note 1)
SYNC frequency
750
45
ps
tCLK_HIGH
tCLK_LOW
36
36
40.7
40.7
48
ns
45
ns
kHz
µs
µs
SYNC period
tSYNC_PERIOD
tSYNC_HIGH
tSYNC_LOW
20.8
1.3
SYNC high pulse width
SYNC low pulse width
Note:
19.5
µs
3
Worst case duty cycle restricted to 45/55
DATA SETUP AND HOLD
Figure 18 Data Setup and Hold (50pF External Load)
Note:
Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9715L.
PARAMETER
SYMBOL
tSETUP
tHOLD
MIN
10
TYP
MAX
UNIT
ns
Setup to falling edge of BITCLK
Hold from falling edge of BITCLK
10
ns
Output valid delay from rising edge of
BITCLK
tCO
15
ns
PD Rev 4.0 December 2007
59
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
