Production Data
WM9715L
COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS)
tRST_LOW
tRST2CLK
RESETB
BITCLK
Figure 21 Cold Reset Timing
Note:
For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active
low period otherwise the device may enter test mode. See AC’97 specification or Wolfson
applications note WAN104 for more details.
PARAMETER
SYMBOL
tRST_LOW
tRST2CLK
MIN
1.0
TYP
MAX
UNIT
µs
RESETB active low pulse width
RESETB inactive to BITCLK startup
delay
162.8
ns
WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS)
Figure 22 Warm Reset Timing
PARAMETER
SYMBOL
tSYNC_HIGH
tRST2CLK
MIN
TYP
MAX
UNIT
µs
SYNC active high pulse width
1.3
SYNC inactive to BITCLK startup
delay
162.4
ns
PD Rev 4.0 December 2007
61
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
