Production Data
WM9715L
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
ALC function select
62h
15:14
ALCSEL
00
ALC / Noise
Gate Control
(OFF)
00 = ALC off (PGA gain set by register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Note: Ensure that RECVOLL and RECVOLR
settings (reg. 1Ch) are the same before
entering this mode
13:11
MAXGAIN
111
PGA gain limit for ALC
111 = +30dB
(+30dB)
110 = +24dB
….(6dB steps)
001 = -6dB
000 = -12dB
8
ALCZC
0
ALC Zero Cross enable (overrides ZC bit in
register 1Ch)
0: PGA Gain changes immediately
1: PGA Gain changes when signal is zero or
after time-out
9:10
ZC
TIMEOUT
11
Programmable zero cross timeout
11 217 x MCLK period
10 216 x MCLK period
01 215 x MCLK period
00 214 x MCLK period
ALC target – sets signal level at ADC input
0000 = -28.5dB FS
60h
15:12
11:8
7:4
ALCL
HLD
DCY
ATK
1011
ALC Control
(-12dB)
0001 = -27.0dB FS
… (1.5dB steps)
1110 = -7.5dB FS
1111 = -6dB FS
0000
ALC hold time before gain is increased.
0000 = 0ms
(0ms)
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
0011
ALC decay (gain ramp-up) time
0000 = 24ms
(192ms)
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
3:0
0010
(24ms)
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
Table 9 ALC Control
PD Rev 4.0 December 2007
23
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
