Production Data
WM9715L
AUDIO ADC
The WM9715L has a stereo sigma-delta ADC to digitize audio signals. The ADC achieves high
quality audio recording at low power consumption. The ADC sample rate can be controlled by writing
to a control register (see “Variable Rate Audio”). It is independent of the DAC sample rate.
To save power, the left and right ADCs can be separately switched off using the PD11 and PD12
bits, whereas PR0 disables both ADCs (see “Power Management” section). If only one ADC is
running, the same ADC data appears on both the left and right AC-Link slots.
HIGH PASS FILTER
The WM9715L audio ADC incorporates a digital high-pass filter that eliminates any DC bias from the
ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by
writing a ‘1’ to the HPF bit (register 5Ch, bit 3).
ADC SLOT MAPPING
By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the
right ADC data appears on slot 4. However, the ADC output data can also be sent to other slots, by
setting the ASS (ADC slot select) control bits as shown below.
REGISTER
ADDRESS
BIT
1:0
LABEL
DEFAULT
DESCRIPTION
5Ch
ASS
00
ADC to slot mapping
Additional
Function
Control
00: Left = Slot 3, Right = Slot 4 (default)
01: Left = Slot 7, Right = Slot 8
10: Left = Slot 6, Right = Slot 9
11: Left = Slot 10, Right = Slot 11
3
HPF
0
High-pass filter disable
0: Filter enabled (for audio)
1: Filter disabled (for DC measurements)
Table 6 ADC Control
PD Rev 4.0 December 2007
19
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