WM9707
Advanced Information
WARM WM9707 RESET
A warm WM9707 reset will re-activate the AC-link without altering the current WM9707 register
values. A warm reset is signalled by driving SYNC high for a minimum of 1µs in the absence of
BIT_CLK.
Within normal audio frames SYNC is a synchronous input. In the absence of BIT_CLK, SYNC is
treated as an asynchronous input used in the generation of a warm reset to the WM9707. The
WM9707 will not respond with the activation of BIT_CLK until SYNC has been sampled low again by
the WM9707. This will preclude the false detection of a new audio frame.
SERIAL INTERFACE REGISTER MAP DESCRIPTION
(See Table 17)
The serial interface bits perform control functions described as follows: The register map is fully
specified by the AC’97 specification, and this description is simply repeated below, with optional
unsupported features omitted.
RESET REGISTER (INDEX 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to their
default values. Reading this register returns the ID code of the part, indication of modem support (not
supported by the WM9707) and a code for the type of 3D stereo enhancement.
The ID decodes the capabilities of the WM9707 based on the following:
BIT
FUNCTION
VALUE ON
WM9707
ID0
ID1
Dedicated Mic PCM in channel
Modem line codec support
Bass and treble control
0
0
ID2
0
ID3
Simulated stereo (mono to stereo)
Headphone out support
0
ID4
1
ID5
Loudness (bass boost) support
18-bit DAC resolution
0
ID6
1
ID7
20-bit DAC resolution
0
ID8
18-bit ADC resolution
1
0
ID9
20-bit ADC resolution
SE4...SE0
Wolfson Microelectronics 3D enhancement
11000
Table 4 Reset Register Function
Note that the WM9707 defaults to indicate 18-bit compatibility.
PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)
These registers manage the output signal volumes. Register 02h controls the stereo master volume
(both right and left channels), Register 04h controls the optional stereo headphone out, and Register
06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the register is
the mute bit. When this bit is set to 1 the level for that channel is set at -∞dB.
ML5 to ML0 is for left channel level, MR5 to MR0 is for the right channel and MM5 to MM0 is for the
mono out channel.
Support for the MSB of the volume level is not provided by the WM9707. If the MSB is written to,
then the WM9707 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes
a 1xxxxx the WM9707 interprets that as x11111. It will also respond when read with x11111 rather
than 1xxxxx, the value written to it. The driver can use this feature to detect if support for the 6th bit is
there or not.
The default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000), which
corresponds to 0dB gain with mute on.
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
20
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
