Advanced Information
WM9707
SLOT 4: PCM RECORD RIGHT CHANNEL
Audio input frame slot 4 is the right channel output of the WM9707’s input Mux, post-ADC.
The WM9707’s ADCs can be implemented to support 16, 18, or 20-bit resolution.
The WM9707 ships out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions
with 0s to fill out its 20-bit time slot.
SLOT 5: OPTIONAL MODEM LINE CODEC
Not supported by WM9707.
SLOT 6: OPTIONAL DEDICATED MICROPHONE RECORD DATA
Not supported by WM9707.
SLOTS 7 TO 12: RESERVED
Audio input frame slots 7 to 12 are reserved for future use and are always stuffed with 0s by the
WM9707.
AC-LINK LOW POWER MODE
The AC-link signals can be placed in a low power mode. When the WM9707’s Powerdown Register
26h, is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to, and
held at a logic low voltage level.
BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to the
Powerdown Register 26h with PR4. When the AC’97 controller driver is at the point where it is ready
to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid
stream in the audio output frame. At this point in time it is assumed that all sources of audio input
have also been neutralised.
The AC’97 controller should also drive SYNC and SDATA_OUT low after programming the WM9707
to this low power, halted mode.
Once the WM9707 has been instructed to halt BIT_CLK, a special wake up protocol must be used to
bring the AC-link to the active mode since normal audio output and input frames can not be
communicated in the absence of BIT_CLK.
WAKING UP THE AC-LINK
There are 2 methods for bringing the AC-link out of a low power, halted mode. Regardless of the
method, it is the AC’97 controller that performs the wake up task.
AC-link protocol provides for a Cold WM9707 Reset, and a Warm WM9707 Reset.
The current Powerdown state would ultimately dictate which form of WM9707 reset is appropriate.
Unless a cold or register reset (a write to the Reset Register 00h) is performed, wherein the WM9707
registers are initialised to their default values, registers are required to keep state during all
Powerdown modes.
Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur
for a minimum of 4 audio frame times following the frame in which the Powerdown was triggered.
When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).
COLD WM9707 RESET
A cold reset is achieved by asserting RESETB for the minimum specified time (1µs). By driving
RESETB low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and
all the WM9707 control registers will be initialised to their default power on reset values.
RESETB is an asynchronous WM9707 input.
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
19
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
