WM9707
Advanced Information
THE WM9707 SAMPLES SYNC ASSERTION HERE
AC’97 CONTROLLER SAMPLES FIRST
SDATA_IN BIT OF FRAME HERE
SYNC
BIT_CLK
CODEC
READY
SLOT (1)
SLOT (2)
SDATA_IN
END OF PREVIOUS AUDIO FRAME
Figure 14 Start of an Audio Input Frame
A new audio input frame begins with a low to high transition of SYNC as shown in Figure 14. SYNC
is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,
AC’97 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link
are aware of the start of a new audio frame. On the next rising of BIT_CLK, AC’97 transitions
SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented
to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC’97 Controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent
sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by the WM9707. SDATA_IN should be
sampled on the falling edges of BIT_CLK.
SLOT 1: STATUS ADDRESS PORT
The status port is used to monitor status for the WM9707 functions including, but not limited to, mixer
settings, and power management.
Audio input frame slot 1 echoes the control register index, for historical reference, for the data to
be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the WM9707 during slot
0).
STATUS ADDRESS PORT BIT ASSIGNMENTS:
Bit (19)
RESERVED (stuffed with 0s)
Bit (18:12)
Control register index (echo of register index for which data is
being returned)
Bit (11:2)
Bit (1:0)
Variable sample rate SLOTREQ bits.
RESERVED (stuffed with 0s)
The first bit (MSB) generated by the WM9707 is always stuffed with a 0. The following 7 bit positions
communicate the associated control register address. The next 10 bits support the AC’97 Rev 2.1
variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by AC’97.
SLOT 2: STATUS DATA PORT
The status data port delivers 16-bit control register read data.
Bit (19:4)
Control register read data (stuffed with 0s if tagged invalid by
WM9701)
Bit (3:0)
RESERVED (stuffed with 0s)
If slot 2 is tagged invalid by the WM9707, then the entire slot will be stuffed with 0s by the WM9707.
SLOT 3: PCM RECORD LEFT CHANNEL
Audio input frame slot 3 is the left channel output of the WM9707’s input Mux, post-ADC.
The WM9707 sends out its ADC output data (MSB first), and stuffs any trailing non-valid bit positions
with 0s to fill out its 20-bit time slot.
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
18
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
