Pre-Production
WM8985
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8985 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from
an existing audio master clock.
Figure shows the PLL and internal clocking on the WM8985.
The PLL can be enabled or disabled by the PLLEN register bit.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1 (01h)
5
PLLEN
0
PLL enable
0 = PLL off
1 = PLL on
Power
management 1
Table 46 PLLEN Control Bit
Figure 38 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure ) can be set using the register bits PLLK and PLLN:
PLLN = int R
PLLK = int (224 (R-PLLN))
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 224 x (8.192 – 8)) = 3221225 = 3126E9h
PP, Rev 3.4, October 2006
79
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
