WM8985
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R36 (24h)
4
PLLPRESCALE
0
0 = MCLK input not divided (default)
PLL N value
1 = Divide MCLK by 2 before input
to PLL
3:0
5:0
PLLN
1000
0Ch
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R37 (25h)
PLLK [23:18]
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
PLL K value
1
R38 (26h)
8:0
8:0
PLLK [17:9]
PLLK [8:0]
093h
0E9h
PLL K Value
2
R39 (27h)
PLL K Value
3
Table 47 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in 48.
MCLK DESIRED
f2
R
N
K
N
K REGISTERS
R38
OUTPUT
(SYSCLK)
(MHz)
(f1)
(MHz)
REGISTER
R36[3:0]
R37
R39
(MHz)
12
12
11.29
12.288
11.29
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
7.5264
8.192
7h
8h
6h
7h
6h
6h
9h
Ah
9h
9h
9h
9h
7h
8h
6h
7h
6h
7h
86C226h
3126E8h
F28BD4h
8FD525h
45A1CAh
D3A06Eh
6872AFh
3D70A3h
2DB492h
FD809Fh
1F76F7h
EE009Eh
86C226h
3126E8h
F28BD4h
8FD525h
B0AC93h
482296h
XX7h
XX8h
XX6h
XX7h
XX6h
XX6h
XX9h
XXAh
XX9h
XX9h
XX9h
XX9h
XX7h
XX8h
XX6h
XX7h
XX6h
XX7h
021h
00Ch
03Ch
023h
011h
034h
01Ah
00Fh
00Bh
03Fh
007h
03Bh
021h
00Ch
03Ch
023h
02Ch
012h
161h
093h
145h
1EAh
0D0h
1D0h
039h
0B8h
0DAh
0C0h
1BBh
100h
161h
093h
145h
1EAh
056h
011h
026h
0E8h
1D4h
125h
1CAh
06Eh
0AFh
0A3h
092h
09Fh
0F7h
09Eh
026h
0E8h
1D4h
125h
093h
096h
13
6.947446
7.561846
6.272
13
12.288
11.29
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
12.288
11.29
6.826667
9.408
12.288
11.29
10.24
9.178537
9.990243
9.122909
9.929697
7.5264
12.288
11.29
12.288
11.29
24
12.288
11.29
8.192
26
6.947446
7.561846
6.690133
7.281778
26
12.288
11.29
27
27
12.288
Table 48 PLL Frequency Examples
PP, Rev 3.4, October 2006
80
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
