WM8985
Pre-Production
Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1
Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that
DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum
threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1
rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the
control interface may take place.
On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the
minimum threshold Vpord_off
.
SYMBOL
Vpora
MIN
0.4
0.9
0.4
0.5
0.4
TYP
0.6
1.2
0.6
0.7
0.6
MAX
0.8
1.6
0.8
0.9
0.8
UNIT
V
V
V
V
V
Vpora_on
Vpora_off
Vpord_on
Vpord_off
Table 2 Typical POR Operation (Typical Simulated Values)
Notes:
1. If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating
level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal
operation when the voltage is back to the recommended level again.
2. The chip will enter reset at power down when AVDD1 or DCVDD falls below Vpora_off or Vpord_off
.
This may be important if the supply is turned on and off frequently by a power management
system.
3. The minimum tpor period is maintained even if DCVDD and AVDD1 have zero rise time. This
specification is guaranteed by design rather than test.
PP, Rev 3.4, October 2006
22
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