WM8985
Pre-Production
Test Conditions
DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Master Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
10
10
ns
ns
ns
ns
tDDA
tDST
tDHT
10
10
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 4 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz,
MCLK= 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
50
20
20
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRC set-up time to BCLK rising edge
LRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACDAT set-up time to BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
tDs
tDD
10
Note:
BCLK period should always be greater than or equal to MCLK period.
PP, Rev 3.4, October 2006
18
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
