Pre-Production
WM8985
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
5
RIN2INPPGA
1
1
Connect RIN pin to right channel input PGA
negative terminal.
Input Signal
Path
0=RIN not connected to input PGA
1=RIN connected to right channel input PGA
amplifier negative terminal.
4
RIP2INPPGA
Connect RIP pin to right channel input PGA
amplifier positive terminal.
Input Signal
Path
0 = RIP not connected to input PGA
1 = right channel input PGA amplifier positive
terminal connected to RIP (constant input
impedance)
3
2
0
0
Reserved. Initialise to 0
L2_2INPPGA
LIN2INPPGA
LIP2INPPGA
Connect L2 pin to left channel input PGA
positive terminal.
Input Signal
Path
0=L2 not connected to input PGA
1=L2 connected to input PGA amplifier positive
terminal (constant input impedance).
1
0
1
1
Connect LIN pin to left channel input PGA
negative terminal.
Input Signal
Path
0=LIN not connected to input PGA
1=LIN connected to input PGA amplifier
negative terminal.
Connect LIP pin to left channel input PGA
amplifier positive terminal.
Input Signal
Path
0 = LIP not connected to input PGA
1 = input PGA amplifier positive terminal
connected to LIP (constant input impedance)
45 (2Dh)
8
7
INPPGAU
N/A
0
INPPGAVOLL and INPPGAVOLR volume do
not update until a 1 is written to
INPPGAUPDATE (in reg 45 or 46)
Input Signal
Path
INPPGAZCL
Left channel input PGA zero cross enable:
0=Update gain when gain register changes
Input Signal
Path
1=Update gain on 1st zero cross after gain
register write.
6
INPPGAMUTEL
INPPGAVOLL
0
Mute control for left channel input PGA:
0=Input PGA not muted, normal operation
Input Signal
Path
1=Input PGA muted (and disconnected from the
following input BOOST stage).
5:0
010000
Left channel input PGA volume
Input Signal
Path
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = 35.25dB
46 (2Eh)
8
7
INPPGAU
N/A
0
INPPGAVOLL and INPPGAVOLR volume do
not update until a 1 is written to
INPPGAUPDATE (in reg 45 or 46)
Input Signal
Path
INPPGAZCR
Right channel input PGA zero cross enable:
0=Update gain when gain register changes
Input Signal
Path
1=Update gain on 1st zero cross after gain
register write.
6
INPPGAMUTER
0
Mute control for right channel input PGA:
0=Input PGA not muted, normal operation
Input Signal
Path
1=Input PGA muted (and disconnected from the
following input BOOST stage).
PP, Rev 3.4, October 2006
103
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
